(1) Field of the Invention
The present invention relates to a multilevel imaging module formed by disposing an imaging semiconductor -chip and a semiconductor control chip in three dimensions, and a method for fabricating the module.
(2) Description of Related Art
In recent years, there are a high demand for size reduction and functional improvement of electronic devices such as cellular phones and digital cameras. To meet this demand, multilevel semiconductor packages formed by stacking electronic components, particularly image sensor chips, and integrated circuit chips for signal processing have been proposed.
For example, an imaging module having a stack package structure for electrically connecting an image sensor to a wiring board is known. This imaging module includes, for example, a board, an envelope, an integrated circuit chip, a spacer, an image sensor chip and a transparent layer. In this imaging module, a signal input terminal is provided on the principal surface of the board, and a signal (input) terminal for connection to the wiring board is provided on the back surface of the board. The wiring board is connected to an external circuit. The image sensor chip is placed over the upper surface of the integrated circuit chip with the spacer interposed therebetween, forms a multilayer structure together with the integrated circuit chip, and is electrically connected to the signal input terminal on the board. The transparent layer is made of transparent glass and covers the upper surface of the envelope and the image sensor chip. The principal surface of the board herein is the surface on which semiconductor devices such as an integrated circuit and light receiving/emitting devices are mounted. The back surface of the board herein is the surface opposite to the principal surface.
Now, a conventional example will be further described.
A module disclosed in Japanese Unexamined Patent Publication No. 2002-354200 has a stack structure in which an integrated circuit chip is mounted on a wiring board and an image sensor chip is stacked over the principal surface of the chip with a spacer interposed therebetween. In this structure, an envelope is bonded to the upper surface of the wiring board and transparent glass is attached to the upper surface of the envelope. The wiring board is provided with, on one surface thereof, a connection terminal for connection to a terminal and a metal fine wire on a semiconductor chip. The connection terminal is connected to an external terminal provided on the other surface of the wiring board through a via and a wire. This external terminal is mounted to a mounting board with solder balls interposed therebetween. In this publication, a structure in which semiconductor chips stacked in two levels are placed in a resin-encapsulated hollow package or an OMPAC (Over Molded Pad Array Carrier) package using a resin board is disclosed.
In Japanese Unexamined Patent Publication No. 2002-296435, as an optical device chip included in a package, a chip provided with light receiving/emitting devices is used. Also disclosed is a method for fabricating an optical communication device characterized in that a package is mounted on a printed circuit board with solder ball terminals having a BGA (Ball Grid Array) structure sandwiched therebetween.